I/O Implementation and Evaluation of Parallel Pipelined STAP on High Performance Computers

This paper presents experimental performance results for a parallel pipeline STAP system with I/O task implementation. In our previous work, a parallel pipeline model was designed for radar signal processing applications on parallel computers. Based on this model, we implemented a real STAP application which demonstrated the performance scalability of this model in terms of throughput and latency. The parallel pipeline model normally does not include I/O task because the input data can be provided directly from radars. However, I/O can also be done through disk le systems if radar data is stored in disks rst. In this paper, we study the eeect on system performance when the I/O task is incorporated in the parallel pipeline model. We used the parallel le systems on the Intel Paragon and the IBM SP to perform parallel I/O and studied its eeects on the overall performance of the pipeline system. All the performance results shown in this paper demonstrated the scalability of parallel I/O implementation on the parallel pipeline STAP system.